Experience: 5 to 10 years in memory layout design including building top level instances with Memory Compilers
Bachelor degree in Electrical Engineering or Physics Engineering minimum
Master’s Degree or PhD in Analog, Mixed-Signal or RF IC design preferred
Advanced knowledge of design rules, yield and reliability issues (EM-IR, HCI and NBTI).
Must have transistor, cell and block level memory layout design hands on experience in either of 3nm/5nm/7nm/10nm/14nm FinFET process technology for memory layout
Knowledge of CMOS semiconductor physics and microfabrication processes and impact of layout on the performance of circuitry in leading edge CMOS/FinFET processes
Working knowledge of SKILL/PERL/TCL shell scripting languages is an asset
Knowledge of LEF will be added advantage
Knowledge or experience of compiler coding is preferred